sorry if basic. simplified version of i'm doing. i'm writing kernel module. when it's running there 2 threads 1 2 different physical cpu. i'm using global variable communication between these threads. strange thing write 1 thread not seen other. reason?
i suspect has memory barrier , maybe cache synchronization, i've tried using smp_wmb() after write, not seem help. , far know can't explicitly control cache synchronization. i'm kinda stuck.
any ideas?
edit: make clear description simplified version.
first of all, you're doing wrong. proper synchronization between cpus quite complicated , architecture specific matter. should use of existing kernel mechanisms thread synchronization. unless have specific performance needs, use spinlocks. then, if needed, may read little bit more different synchronization mechanisms , find 1 best suits workload.
to answer question more directly - there @ least 2 issues may facing here: 1. instruction reorder compiler taken care of compiler barriers (i.e. barrier()
). 2. out-of-order execution cpu , cache coherency taken care of memory barriers.
details architecture , usecase specific didn't provide code or architecture details analyze. might required use @ least , of barrier()
, smp_wmb()
, smp_rmb()
, smp_read_barrier_depends()
.
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